A pipeline type A/D converter includes a plurality of A/D converter circuits, and each of the A/D converter circuits bears a very important function. The power consumed by these A/D converter circuits occupies a large proportion of the entire power consumption. Such A/D converter circuits constituting a pipeline A/D converter are required to perform operational amplification operation including multiplication and addition/subtraction for an input signal.
As an exemplary configuration, such an A/D converter circuit includes a voltage comparator for comparing a supplied analog input voltage with a reference voltage, a voltage generator for generating a reference voltage used for addition/subtraction, an amplifier for operationally amplifying an input signal, and the like.
FIG. 6 shows a conventional A/D converter circuit as a component of a pipeline A/D converter. This conventional A/D converter circuit is described in Non-patent Literature 1. The A/D converter circuit 100 shown in FIG. 6 includes a sub-A/D converter 2a, a sub-D/A converter 3a, an amplifier 1a, a first capacitor C11, a second capacitor C12 and five switches SW1, SW2, SW3, SW4 and SW5.
The operation of the A/D converter circuit having the circuit configuration described above can be divided into two different periods: a sampling period and an amplification period. First, the sampling period during which an input signal is sampled will be described. In the sampling period, the switch SW1 is switched to position a (the side of input of an input signal VIN), two switches SW2 and SW5 are turned ON, and the remaining two switches SW3 and SW4 are turned OFF. In this state, the analog input signal VIN inputted via the input terminal is connected to the sub-A/D converter 2a and the first and second capacitors C11 and C12, but not connected to the output terminal of the amplifier 1a. Once the sampling period is terminated, the three switches SW1, SW2 and SW3 are turned OFF.
In the subsequent amplification period, the switch SW1 is switched to position b (the side of the sub-D/A converter 3a), two switches SW3 and SW4 are turned ON, and the remaining two switches SW2 and SW5 are turned OFF. In this state, the output terminal of the sub-D/A converter 3a is connected with the first capacitor C11, and the output terminal of the amplifier 1a is connected with the second capacitor C12. At this time, the non-inverting input terminal of the amplifier 1a is virtually grounded. Once the amplification period is terminated, the three switches SW1, SW3 and SW4 are turned OFF. These entire switch operations are performed synchronously.
More specifically, during the sampling period, the analog input signal VIN is applied to the first and second capacitors C11 and C12 to allow charge to be stored in these capacitors. Also, the sub-A/D converter 2a A/D-converts the analog input signal VIN based on a predetermined reference voltage. Subsequently, the sub-D/A converter 3a D/A-converts the digital input signal A/D-converted by the sub-A/D converter 2a, to determine a reference voltage used for addition/subtraction in the next amplification period.
In the subsequent amplification period, the output terminal of the sub-D/A converter 3a is connected with the first capacitor C11, and the output terminal of the amplifier 1a is connected with the second capacitor C12. During this time, since the non-inverting input terminal of the amplifier 1a is virtually grounded, charge corresponding to the reference voltage as the output of the sub-D/A converter 3a is stored in the first capacitor C11. As a result, the remaining charge obtained by subtracting the charge amount existing in the first capacitor C11 from the charge stored in the first capacitor C11 during the sampling period is shifted to the second capacitor C12.
In the series of operations described above, by adjusting the capacitance ratio between the first and second capacitors C11 and C12, the input signal voltage VIN can be subjected to amplification and addition/subtraction with an arbitrary scaling factor, and thus a desired input/output transmission function can be obtained.
In a pipeline A/D converter having a plurality of such A/D converter circuits 100 connected to one another, while one A/D converter circuit 100 is in the amplification period, the next-stage A/D converter circuit is in the sampling period, in which the output terminal of the preceding stage amplifier 1a is connected with the input terminal of the next-stage A/D converter circuit. Therefore, the output terminal of the preceding stage amplifier 1a is connected with the next-stage capacitor C13 including the next-stage sampling capacitors (first and second capacitors C11 and C12) and the like during the amplification period. With the next-stage capacitor C13 being connected, the A/D converter circuit is required to converge the output voltage to a predetermined operation target value. Therefore, since the load capacitance of the A/D converter circuit becomes very large, a high-performance amplifier 1a is necessary.
For the reason described above, to implement a high-resolution pipeline A/D converter operating at high speed, it is necessary to enhance the accuracy, gain and speed of the A/D converter circuit.
Non-Patent Literature 1: Andrew M. Abo et al., “A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter”, IEEE Journal of Solid-State Circuits, Vol. 34, No. 5, May 1999